Convolution Operation Implemented in FPGA Structures for Real-Time Image Processing
نویسندگان
چکیده
Addition is an essential operation for the convolution (or FIR filters). In FPGAs, addition should be carried out in a standard way employing ripple-carry adders (rather than carry-save adders), which complicates search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of addition inputs have been considered e.g. correlation between inputs. These parameters are specified in different ways for different convolver architectures: Multiplierless Multiplication, Look-Up Table based Multiplication, Distributed Arithmetic. Furthermore, different optimisation techniques: Exhausted Search and Simulated Annealing have been implemented, and as a result. Otherwise, the Exhausted Search should be employed for the number of the addition inputs n≤8, or the Simulated Annealing for n>8. Employing the Simulated Annealing gives about 10-20% area reduction in comparison to the Greedy Algorithm. This paper is a part of the research on the AuToCon – Automated Tool for generating Convolution in FPGAs.
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